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Issues and possible solutions — 12 Principles of green chemistry- nuclear accidents and holocaust, case studies. Public awareness. Environmental Pollution or problems cannot be solved by mere laws. Public participation is an important aspect which serves the environmental Protection.

One will obtain knowledge on the following after completing the course. Gilbert M. I and II, Enviro Media. Cunningham, W. Cooper, T. Dharmendra S.


Yu-Cheng Liu, Glenn A. Doughlas V. Linear and Circular Convolutions 3. Spectrum Analysis using DFT 4. FIR filter design 5. IIR filter design 6. Multirate Filters 7. Study of architecture of Digital Signal Processor 9. MAC operation using various addressing modes Linear Convolution Circular Convolution FFT Implementation Waveform generation Signal Sampling and reconstruction 2.

Time Division Multiplexing 3. AM Modulator and Demodulator 4. FM Modulator and Demodulator 5. Pulse Code Modulation and Demodulation 6. Delta Modulation and Demodulation 7. Line coding schemes 9. Error control coding schemes - Linear Block Codes Simulation Communication link simulation Basic arithmetic and Logical operations 2.

Move a data block without overlap 3. Code conversion, decimal arithmetic and Matrix operations. Floating point operations, string manipulations, sorting and searching 5. Password checking, Print RAM size and system date 6. Traffic light control 8. Stepper motor control 9. Digital clock Key board and Display Printer status Serial interface and Parallel interface Basic arithmetic and Logical operations UNIT IV DIRECTING 9 Foundations of individual and group behaviour — motivation — motivation theories — motivational techniques — job satisfaction — job enrichment — leadership — types and theories of leadership — communication — process of communication — barrier in communication — effective communication — communication and IT.

Stephen P. Stephen A. Patterson and John L. Carl Hamacher, Zvonko G.

Varanesic and Safat G. Vincent P. Heuring, Harry F. John P. Larry L. Peterson, Bruce S. James F. Kurose, Keith W. Behrouz A. Jan Rabaey, Anantha Chandrakasan, B. Weste, K.

A = 0, P = 0, Q = AB, R = B : A = 1, C = 1, P = 1, Q = MUX, R = XOR

Jacob Baker, Harry W. Matching — Baluns, Polarization mismatch, Antenna noise temperature, Radiation from oscillating dipole, Half wave dipole. Folded dipole, Yagi array.

Edward C. Jordan and Keith G. Robert S. Implementation of Stop and Wait Protocol and sliding window 3.

Implementation and study of Goback-N and selective repeat protocols 4. Study of Socket Programming and Client — Server model 6. Network Topology - Star, Bus, Ring 9. Implementation of distance vector routing algorithm Implementation of Link state routing algorithm Encryption and decryption. HDL based design entry and simulation of simple counters, state machines, adders min 8 bit and multipliers 4 bit min.

Critical paths and static timing analysis results to be identified. Identify and verify possible conditions under which the blocks will fail to work correctly. Hardware fusing and testing of each of the blocks simulated in I. Use of either chipscope feature Xilinx or the signal tap feature Altera is a must. Design and simulation of a simple 5 transistor differential amplifier. Layout generation, parasitic extraction and resimulation of the circuit designed in I 6.

Synthesis and Standard cell based design of an circuits simulated in 1 I above. Identification of critical paths, power consumption.

Analysis of results of static timing analysis. Writing job applications — cover letter — resume — emails — letters — memos — reports — blogs — writing for publications.

Learners are to be encouraged to blog, tweet, text and email employing appropriate language. Students should write a report on a regular basis on the activities conducted, focusing on the details such as the description of the activity, ideas emerged, learning outcomes and so on. At the end of the semester records can be evaluated out of 20 marks.

Interview — mock interview can be conducted on one-on-one basis. Speaking — example for role play: Marketing engineer convincing a customer to buy his product. Presentation — should be extempore on simple topics. Discussion — topics of different kinds; general topics, case studies and abstract concept.

Robert M Sherfield and et al. Pearson Education, Tuning screw, Stub and quarter wave transformers. David M. John M. Jonathan W. Raymond J. Buhr, Donald L.

Krishna, Kang G. Study of ARM evaluation system 2. Interfacing real time clock and serial port. Interfacing keyboard and LCD. Flashing of LEDS. Interfacing stepper motor and temperature sensor. Implementing zigbee protocol with ARM. Embedded trainer kits with ARM board 10 No. Embedded trainer kits suitable for wireless communication 10 No. Understand the working principle of optical sources, detector, fibers and microwave components 2.

Develop understanding of simple optical communication link. Learn about the characteristics and measurements in optical fiber 4. Know about the behavior of microwave components. Mode Characteristics of Fibers 3. Measurement of connector and bending losses 4. Fiber optic Analog and Digital Link- frequency response analog and eye diagram digital 5. Numerical Aperture determination for Fibers 6. Reflex klystron or Gunn diode characteristics and basic microwave parameter measurement such as VSWR, frequency, wavelength.

Directional Coupler Characteristics. Radiation Pattern of Horn Antenna. Trainer kit for determining the mode characteristics, losses in optical fiber.

Kit for measuring Numerical aperture and Attenuation of fiber - 2 Nos 5.

Microwave test Bench at X band to determine Directional coupler characteristics. Van Nee, R. System architecture, protocol architecture, physical layer, MAC layer, Anurag Kumar, D. To train the students in preparing project reports and to face reviews and viva voce examination. The students in a group of 3 to 4 works on a topic approved by the head of the department under the guidance of a faculty member and prepares a comprehensive project report after completing the work to the satisfaction of the supervisor.

The progress of the project is evaluated based on a minimum of three reviews. The review committee may be constituted by the Head of the Department. A project report is required at the end of the semester. The project work is evaluated based on oral presentation and the project report jointly by external and internal examiners constituted by the Head of the Department. Khandpur, R. Joseph J. Carr and John M. Proakis, Dimitris G. Dwight F.

Sophocles J. Operating system overview-objectives and functions, Evolution of Operating System.

Andrew S. Upon completion of the course, the student should be able to: Mikell P. Weiss G. Ghosh, Control in Robotics and Automation: Klafter R. Mc Kerrow P. Groover, Mitchell Weiss, Roger N. Nagel Nicholas G. Gonzaleaz R. Wilbur L. Pritchard, Hendri G. Suyderhoud, Robert A. Bruce R. Tri T. Robert G. Michael L. Bushnell and Vishwani D. Upon completion of the course, students will: Cary R. Middleton, D. Spitzer, C. Introduction, characteristics- learning methods — taxonomy — Evolution of neural networks- basic models - important technologies - applications.

Fuzzy logic: Introduction - crisp sets- fuzzy sets - crisp relations and fuzzy relations: Genetic algorithm- Introduction - biological background - traditional optimization and search techniques - Genetic basic concepts.

A fusion approach of multispectral images with SAR, optimization of traveling salesman problem using genetic algorithm approach, soft computing based hybrid fuzzy controllers. Jang, C. Sun and E. Sivanandam and S. Rajasekaran and G. George J. Klir, Ute St. David E. James A. Freeman, David M. Detection of Discontinuities—Edge Linking and Boundary detection — Region based segmentation- Morphological processing- erosion and dilation.

Upon successful completion of this course, students will be able to: Rafael C. Gonzales, Richard E. Gonzalez, Richard E. Woods, Steven L. Anil Jain K. Malay K. Architecture of a large vocabulary continuous speech recognition system — acoustics and language models — n-grams, context dependent sub-word units; Applications and present status. Concatenative and waveform synthesis methods, sub-word units for TTS, intelligibility and naturalness — role of prosody, Applications and present status.

Steven W. Features - Components - Tags - Struts: Configuration Settings - Mapping persistent classes - Working with persistent objects - Concurrency - Transactions - Caching - Queries for retrieval of objects - Spring: Framework - Controllers - Developing simple applications.

Given an electronic system PCB or integrated circuit design specifications, the student should be in a position to recommend the appropriate packaging style to be used, and propose a design a design procedure and solution for the same. Rao R. Henry W. Andrew N. James L. Web links www. Thomas W. Rondeau, Charles W. Bruce A. Ian F. Alexander M. Wyglinski, Maziarnekovee, Y. Merrill I. Peyton Z. Wilson and J. Matthew M. Applications of Ad Hoc and Sensor networks.

VLSI Design (AU for 4th Semester ECE) Book Information:

Design Challenges in Ad hoc and Sensor Networks. Siva Ram Murthy, and B. Manoj, "Ad Hoc Wireless Networks: Chand and Company, New Delhi. Kurose and W. Steimnetz, K. Mike W. Charles B. Charles E. Harris, Michael S. Pritchard and Michael J. Laura P. Single stage amplifier as comparator, cascaded amplifier stages as comparator, latched comparators. Public key cryptography: Intruder — Intrusion detection system — Virus and related threats — Countermeasures — Firewalls design principles — Trusted systems — Practical implementation of cryptography and security.

Web Security: Upon Completion of the course, the students should be able to: UNIT V. Dale H. Besterfiled, et at. James R. Evans and William M. B and Gopal. Keywords: Reversible logic, Garbage output, Quantum computing, Bijective mapping, Logical reversibility.

Introduction Reversible logic design is extensively motivated in recent years due to its energy and information lossless design.

Conventional irreversible logic gates dissipate heat for every single bit loss during their operation. Based on R. Landauers theory in , the loss of one bit information dissipates KTln2 joules of energy. This loss cannot be avoided if the circuit comprises of irreversible logic gates.

In C. Bennett demonstrated that this KTln2 joules dissipation can be avoided if the circuit is reversible. So this power dissipation issue can be overcome by using reversible logic gates instead of conventional irreversible logic gates in a circuit.

A gate or circuit is reversible if it does not lose any information and allows one to uniquely recover input vector from the output vector and vice versa. In reversible logic gates there is one to one mapping between input and output i.

This bijective mapping prevents the loss of information which is main reason for power dissipation in irreversible logic. The reversible gate output which is not used is called Garbage output. Extra Inputs which are used in reversible gate to make it reversible is called Constant or Garbage input. Such as Less number of reversible logic gates are used to design reversible circuit Less number of constant or garbage input should be used to make the gate reversible Garbage output should be minimum Fan out is not allowed in reversible logic gate.

The fan out of each gate is equal to one.

A copying gate is used if more fan out are required The purpose of this paper is to propose new reversible gate using Gate Diffusion Input GDI Technique. The primary objective of this proposed gate produces optimum power product Product of power and delay PDP and quantum cost with compared to the existing counterpart. The proposed primitive structure is designed to operate in Corresponding author R.

Uma, et al. Figure 1. Section IV presents the performance issues with respect to its counterpart. Section V presents the discussion.

Finally the conclusion is presented in section VI. Proposed Primitive Reversible Primitive Cells A reversible gate has equal number of inputs and outputs and one-to-one mappings between input vectors and output vectors; so that, the input vector states can be always uniquely reconstructed from the output vector states.

Several reversible gates have been reported in [14,]. The proposed gate consists of 3 input and 3 output reversible blocks. The logic diagram and truth table of the proposed reversible gates are shown in gure 1. The primary issues in the design of adder cells are area, delay and power dissipation.

The circuit is realized as two stage network, stage1 and stage2 respectively. Assume that the input capacitance of 10pf on each input and it will drive the output capacitance with a maximum of 10pf. From this observation the delay of the circuit vary with change in the input and output capacitance value. All the full adders are simulated with multiple design corners TT, FF, FS, and SS to verify that operation across variations in device characteristics and environment.

The test bed is supplied with a nominal voltage of 2V in steps of 0. To establish an unbiased testing environment, the simulations have been carried out using a comprehensive input signal pattern, which covers every possible transition for a 1- bit full adder. The three inputs to the full adder are A, B, C and all the test vectors are generated and have been fed into the adder cell. All transitions from an input combination to another total 8 patterns, , , , , , , , have been tested, and the delay at each transition has been measured.

The average has been reported as the cell delay. The power consumption is also measured for these input patterns and its average power has been reported in Table 3. Figure 3. The performance of all the full adders has been analyzed in terms of delay, transistor count and power dissipation. It is observed that adder designed with XOR and MUX has the least delay, transistor count and power dissipation when compared to other combinations of gate.

The power-delay product all the full adders is shown in Figure 5. Figure 4. Simulation result of adders in terms Figure 5. So the primitive of this adder cell is implemented with multiplexer and this module is incorporated with existing adder topologies. This device was chosen because the Spartan3E families of Field-Programmable Gate Arrays FPGAs are specifically designed to meet the needs of high volume, cost-sensitive consumer electronic applications.

These Spartan-3E FPGA enhancements, combined with advanced 90 nm process technology, deliver more functionality and bandwidth. Table 4 contains the results obtained. It is noticed that delay, area and power delay product are less when compared to the normal expression. So the adder realized with MUX and XOR is considered to be the optimized adder in terms of delay, transistor count and power dissipation.

Its performances have been analyzed and reported in section 4. In case of slice utilized there is no change occurs for RCA and CLA hence its distribution is shown as single red line in the chart Figure 7b.

From AT chart Figure 7c it is noticed that the AT value is large for 64 bit carry select adders and adders like ripple carry adder, carry look ahead adder and carry increment adder have less AT Value. From PD distribution Figure 7d less power dissipation occurs for carry increment and ripple carry adders, maximum dissipation occurs for carry save and carry skip adders.

According to the presented results, the adder topology which has the best compromise between area, delay and power dissipation are carry look-ahead and carry increment adders and they are suitable for high performance and low-power circuits. The fastest adders are carry select and carry save adders with the penalty of area.

The simplest adder topologies that are suitable for low power applications are ripple carry adder, carry skip and carry bypass adder with least gate count and maximum delay. Figure 7. Delay Chart Figure 7. AT Value Chart Figure 7.

VLSI Design (AU for 4th Semester ECE)

PT Value Chart 7. Technology independent logic optimization is used to design 1-bit full adder with 20 different Boolean expressions and its performance was analyzed in terms of transistor count, delay and power dissipation using Tanner EDA with TSMC MOSIS nm technology. From this analysis XOR and MUX based expression provides low transistor count, minimum delay and minimum power dissipation when compared to other logic equations.

The worst case full adder construction is not using NOR gate which occupies large transistor count, dissipates large power and has longer delay.

Logical effort delay model to estimate the parasitic delay is also presented. Using the optimized expression the primitive adder cell is implemented with multiplexer and this module is incorporated with existing adder topologies like ripple carry adder, carry look-ahead adder, carry skip adder, carry select adder, carry increment adder and carry save adder and its performance is analyzed in terms of area slices used and maximum combinational path delay as a function of size.

The comparison and its simulation results have been presented. Based on the comparison it is observed that number of slices occupied, power dissipation and delay are less using the optimized expression. The work presented in this paper gives more insight and deeper understanding of constituting modules of the adder cell to help the designers in making their choices.

Karandikar and Sachin S.Finally the conclusion is presented in section VI. Dharmendra S. Implementation of Stop and Wait Protocol and sliding window 3. Methods of starting of synchronous motors — Torque equation — V curves — Synchronous motors.

Class A Power Amplifier. Pulse Code Modulation and Demodulation 6. The primary objective of this proposed gate produces optimum power product Product of power and delay PDP and quantum cost with compared to the existing counterpart.