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CMOS ANALOG CIRCUIT DESIGN PHILLIP E ALLEN PDF

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CMOS Analog Circuit Design. OD. Second Edition. Phillip E. Allen. Georgia Institute of Technology. Douglas R. Holberg. Cygnal Integrated Products, Inc. Allen and Holberg - CMOS Analog Circuit Design. Page I .. (e). (f). (g) n-well n-well. Si3N4. Figure The major CMOS process steps (cont'd). principles presented in CMOS Analog Circuit Design come directly from the authors' Phillip E. Allen, Douglas R. Holberg by P. E. Allen Free PDF d0wnl0ad .


Cmos Analog Circuit Design Phillip E Allen Pdf

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CMOS ANALOG. CIRCUIT DESIGN. INTERNATIONAL SECOND EDITION. PHILIP E. ALLEN. DOUGLAS R. HOLBERG. Not for Sale in the U.S.A. or Canada. Third EditionCMOS Analog Circuit Design Phillip E. Allen Professor Emeritus, Georgia Allen, Phillip E._ Holberg, Douglas R-CMOS Analog Circuit Design- Oxford University .. A complete solutions manual to all problems in PDF format. Allen, Holberg - CMOS Analog Circuit Design second resourceone.info - Ebook download as PDF File .pdf) or read book online. Phillip Allen short course notes.

The analysis of a circuit, illustrated in Fig. An important characteristic of the analysis process is that the solution or proper- ties are unique. On the other hand, the synthesis or design of a circuit is the process by which one starts with a desired set of properties and finds a circuit that satisfies them.

In a design problem the solution is not unique, thus giving opportunity for the designer to be creative. Consider the design of a 1.

This resistance could be real- ized as the series connection of three 0. All would satisfy the requirement of 1. The differences between integrated and discrete analog circuit design are important.

Unlike integrated circuits, discrete circuits use active and passive components that are not on the same substrate. A major benefit of components sharing the same substrate in close prox- imity is that component matching can be used as a tool for design. Another difference between the two design methods is that the geometry of active devices and passive compo- nents in integrated-circuit design is under the control of the designer. This control over geom- etry gives the designer a new degree of freedom in the design process.

A second difference is due to the fact that it is impractical to breadboard the integrated-circuit design.

Allen, Holberg - CMOS Analog Circuit Design second edition.pdf

Another difference between integrated and discrete analog design is that the integrated-circuit designer is restricted to a more limited class of components that are compatible with the tech- nology being used. The task of designing an analog integrated circuit includes many steps. The major steps in the design process are: Definition 2.

Synthesis or implementation 3. Simulation or modeling. These steps are crucial since they determine the perform- ance capability of the design. At this point. Once satisfied with this performance.

Geometrical description 5. When these steps are completed. The next step is to simulate the circuit to predict the performance of the circuit.

Fabrication 7. Testing and verification The designer is responsible for all of these steps except fabrication. Simulation including the geometrical parasitics 6. This geometrical description typically consists of a computer database of variously shaped. The first steps are to define and synthesize the function. As stated earlier. Analog integrated-circuit design can also be characterized from the viewpoint of hierar- chy.

If the designer has not carefully considered this step in the overall design process. Computer simulation techniques have been developed that have several advantages. The format of the design description is the way in which the circuit is specified. After fabrication. If results are satisfactory. These advantages include: The geometrical description obviously uses the geometrical format.

For example. Table 1. As mentioned earlier. In accomplishing the design steps described above.

CMOS Analog Circuit Design Allen Holberg 3

The design- er must be able to describe the design in each of these formats. It is expressed in terms of device specifications. Chapters 2 and 3 deal with CMOS technology and models. The design. This book has been organized to emphasize the hierarchical viewpoint of integrated- circuit design. Device characterization methods are covered in Appendix C. The designer must also be able to characterize the actual model parameters in order to confirm the assumed model parameters.

The circuit level is the next higher level of design and can be expressed in terms of devices. In order to design CMOS analog integrated circuits the designer must understand the technology. Before starting a design. At the device level. The highest level of design is the systems level—expressed in terms of circuits. Some of the divid- ing lines between the various levels will at times be unclear. Modeling is a key aspect of both the synthesis and simulation steps and is covered in Chapter 3.

The device level is the lowest level of design. Chapters 4 and 5 cover circuits consisting of two or more devices that are classified as simple circuits. These simple circuits are used to design more complex circuits. The conventions chosen are consistent with those used in undergraduate electronics texts and with the standards proposed by technical societies.

The first item of importance is the notation the symbols for currents and voltages. The symbols shown in Figs. It will be important to know where the bulk of the MOS transistor is con- nected when it is used in circuits.

Most of these symbols will already be familiar to the reader. This notation will be of help when modeling the devices. The second item to be discussed here is what symbols are used for the various compo- nents. Signals will generally be designated as a quantity with a subscript. This model will be developed in terms of the total instantaneous variables iD. If the bulk is not connected to the source. The International System of Units has been used throughout. The quantity and the subscript will be either uppercase or lowercase according to the convention illustrated in Table 1.

For biasing pur- poses. Every effort has been made in the remainder of this book to use the conventions here described.

Most often. Although the transistor operation will be explained later. Idm id ID iD t. The gains of each of these controlled sources are given by the symbols Av. G G b Enhancement p-channel transistor with bulk connected to the source. Figures 1. One advantage is due to the fact that digital circuitry is easily implemented in the small- est geometry processes available.

Another advantage relates to the additional degrees of freedom available in digital signal processing e. These are not used much above 30 GHz because of the difficulties in performing even the simplest forms of signal processing at higher frequencies. The general subject of analog signal processing includes most of the circuits and systems that will be presented in this text. The first block of Fig.

To address any particular application area illustrated in Fig 1. At the low end are seismic signals. The advantages of performing signal processing in the digital domain are numer- ous. The first step in the design of an analog signal-processing system is to examine the spec- ifications and decide what part of the system should be analog and what part should be digi- tal. A graph of the operating frequency of a variety of signals is given in Fig. In most cases. It could be a speech signal.

Additional advantages lie in the ability to easily program digital devices. In a signal-processing system. In the past. At the other extreme are microwave sig- nals. The next block of the analog signal processor is a digital signal processor.

Bandwidth requirements and speed are not the only considerations when deciding which technology to use for an integrat- ed circuit IC addressing an application area. In this case. Other considerations are cost and integration. The zeros of the filter are real and symmetrical about the imaginary axis.

The locations of the zeros relative to the locations of the poles are programmable and are designed to boost filter gain at high frequencies and thus narrow the width of the read pulse. After amplification. In a typical application. This dif- ferential read pulse is first amplified by a variable gain amplifier VGA under control of a real-time digital gain-control loop.

The device employs partial response maximum likelihood PRML sequence detec- tion when reading data to enhance bit-error-rate versus signal-to-noise ratio performance.

This control voltage is applied to the gate of an n-channel transistor in each of the transconduc- tance stages. All capacitors in the low-pass filter are constructed identically. The conductance of each of these transistors determines the overall conductance of its associated stage and can be varied continuously by the control voltage.

While the relative pole arrangement is fixed. The control voltage. The low-pass filter is constructed from transconductance stages gm stages and capaci- tors. A one-pole prototype illustrating the principles embodied in the low-pass filter design is shown in Fig. The second frequency response control mechanism is via the digital control of the value of the capacitors in the low-pass filter.

In write mode. To the extent that the circuit elements in the low-pass filter match those in the master filter. The detector anticipates linear intersymbol interference and after processing the received sequence of values deduces the most likely transmitted sequence i.. The outputs from the comparators are passed through a block of logic that checks for invalid patterns.

As illustrated in Fig. Because these errors can be measured only when signal pulses occur. The write path is illustrated in detail in Fig. The digital gain. The out- puts of this block are then encoded into a 6-bit word. If the data written to the disk were randomized before being encoded. By forcing the oscillator to be phase and frequency locked to an external frequency reference through variation of the VCON terminal voltage.

The heart of the read channel IC is the sequence detector. The data can optionally be randomized before being sent to the. The bit stream from the sequence detector is passed to the run-length-limit- ed RLL decoder block. When enabled. A write clock is synthesized to set the data rate by a VCO placed in a phase-locked loop.

Using the randomizer ensures that bit patterns that may be difficult to read occur no more frequently than would be expected from random input data. Encoded data are passed to the write precompensation circuitry. Normally the signal from one delay line is used to clock the channel data to the output drivers. The values for M and N can each range from 2 to While linear bit-shift effects caused by intersymbol interference need not be compensated in a PRML channel.

The synthesized write clock is input to two delay lines. Input pulses are qualified with a programmable threshold comparator such that a pulse is detected only for those pulses whose peak amplitude exceeds the threshold. An asynchronous bit detector is included to detect the servo data information and address mark.

The servo channel circuitry. There are three main functional blocks in the servo section: The output of the peak detector is compared to a full-scale reference and integrated to control the VGA gain.

The servo bit detector provides outputs indicating both zero-crossing events and the polarity of the detected event. To avoid the need for timing acquisition. The circuit was fabricated in a single-polysilicon. The burst detec- tor is designed to detect and hold the peak amplitude of up to four servo positioning bursts. The peak detector either charges or dis- charges a capacitor. All blocks are powered down between servo fields to conserve power.

The amount of delay is pro- grammable. The peak amplitude at the output of the high-pass filter is detected with a rectifying peak detector. This second delay line is current-starved. The relationship between gain and control voltage for the VGA is an exponential one. The AGC loop feedback around the VGA forces the output of the high-pass filter to a constant level during the servo preamble. It is strongly recommend- ed that the reader refer to Table 1. The difference between analysis and design was dis- cussed.

The first section also presented an overview of the text and showed in Table 1. Additional topics concerning the subject in this section will be given in the text at the appro- priate place.

Section 1. The choice of sym- bols and terminology has been made to correspond with standard practices and definitions. Understanding these topics is important to avoid confusion in the presentation of the various subjects. The reader may also wish to review other subjects. Digitize the sinusoid given in Fig.

Figure P1. The important concepts of circuit application. Before beginning the study of the following chapters. It covers the subject of circuit analysis for analog circuit design. Use the nodal equation method to find 1. Use the source rearrangement and substitu- 5 tion concepts to simplify the circuit shown 4 3 2 in Fig.

The example emphasized the hierarchical structure of the design and showed how the subjects to be presented in the following chapters could be used to implement a complex design.

Laplace and z-transform theory. The boundaries between the analog and digital parts of the circuit depend on the application. Using Eq. Problems 1. The objective of most analog circuits was seen to be the implementation of some sort of analog signal pro- cessing. Process the sinusoid in Fig. June IEEE Int. Banu and Y.

Use the Miller simplification technique described in Appendix A to solve for the — — output resistance. Yee et al. Use the circuit-reduction technique to solve results. Solid-State Circuits. References 17 1. Solid-State Circuits Conf. Solid- State Circuits. The objective is to be able to appreciate the limits of the MOS circuit models and to understand the physical constraints on electrical per- formance.

There are numerous references that develop the details of the physics of MOS device operation [7. Processes that com- bine both CMOS and bipolar BiCMOS have proven themselves to be both a technological and market success where the primary market force has been improved speed for digital cir- cuits primarily in static random-access memories. By the end of the s. For many years the dominant silicon integrated- circuit technology was bipolar.

This chapter covers various aspects of the CMOS process from a physical point of view. This book focuses on the use of CMOS for analog and mixed- signal circuit design. In order to understand CMOS technology. At this same time. Oxidation is the process by which a layer of silicon dioxide SiO2 is formed on the surface of the silicon wafer. This thickness is determined primarily by the physical strength requirements.

The means of defining the area of the semiconductor subject to processing is called photolithography. Oxidation The first basic processing step is oxide growth or oxidation [12].

The cylindrical crystals are sliced into wafers that are approximately 0.

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When the crystals are grown. All processing starts with single-crystalline silicon material. The oxide grows both into as well as on the silicon surface. A second method. The substrate is the starting material in wafer form for the fabrication process. Although epi wafers are more expensive.

The resulting crystals are cylindrical and have a diam- eter of 75— mm and a length of 1 m. Most of the material is grown by a method based on that developed by Czochralski in The six basic processing steps that are applied to the doped silicon wafer to fabricate semiconductor components oxidation. In order to understand the fabrication process.

The process steps described here include oxidation. This topic is covered in Appendix B and should be studied along with Chapter 2. An alternative to starting with a lightly doped silicon wafer is to use a heavily doped wafer that has a lightly doped epitaxial epi on top of it where subsequent devices are formed.

There are two methods for growing such crystals [9]. Successful analog circuit design is tightly coupled with the physical layout. The concentration profile of the impurity in the semiconductor is a function of the concentration of the impurity at the surface and the time in which the semiconductor is placed in a high-temperature environment.

The infinite-source and finite-source diffusions are typical of predeposition and drive-in diffusions. The crossover between the prediffusion impurity level and the diffused impurities of the opposite type defines the semiconductor junction. There is a maximum impurity concentra- tion that can be diffused into silicon depending on the type of impurity. The drive-in diffusion follows the deposition diffusion and is used to drive the impurities deeper into the semiconductor.

The object of a predeposition diffusion is to place a large concentra- tion of impurities near the surface of the material. Diffusion takes place at temperatures in the range of — 8C in the same way as a gas diffuses in air. NB is the prediffusion impurity concentration of the semiconductor. Silicon dioxide 0. The distance between the surface of the semiconductor and the junction is called the junction depth. The second type of diffusion assumes that there is a finite source of impurities at the surface of the material initially.

This junction is between a p-type and an n-type material and is simply called a pn junction. Oxidation takes place at temperatures ranging from 8C to 8C. Typical junction depths for diffusion can range from 0.

The oxide thickness. This maximum concentration is due to the solid solubility limit. At t 5 0 this value is given by N0.

Ion implantation is the process by which ions of a particular dopant impurity are accelerated by an electric field to a high velocity and physically lodge. The impurity pro- file for an infinite-source impurity as a function of diffusion time is given in Fig. Ion Implantation The next basic processing step is ion implantation and is widely used in the fabrication of MOS components [ One type of diffusion assumes that there is an infinite source of impurities at the surface N0 cm23 during the entire time the impurity is allowed to diffuse.

Diffusion The second basic processing step is diffusion [13]. There are two basic types of diffusion mecha- nisms. In both cases. Diffusion in semiconductor material is the movement of impurity atoms at the surface of the material into the bulk of the material.

This damage can be repaired by an annealing process in which the temperature of the semicon- ductor after implantation is raised to around 8C to allow the ions to move to electrically active locations in the semiconductor crystal lattice.

The path of each ion depends on the collisions it experiences. An alternative method to address channeling is to implant through silicon dioxide. Unlike ion implan- tation. Ion implantation can be used in place of diffusion since in both cases the objective is to insert impurities into the semiconductor material. Ion implantation has several advantages over thermal diffusion.

Reproducibility is very good. A second advantage is that ion implantation is a room-temperature process. A third advantage is that it is possible to implant through a thin layer. For exam- ple. The ion-implantation process causes damage to the semiconductor crystal lattice. The average depth of penetration varies from 0.

Deposition The fourth basic semiconductor process is deposition. Deposition is the means by which films of various materials may be deposited on the silicon wafer. These films may be deposited using several techniques, including deposition by evaporation [16], sputtering [17], and chemical- vapor deposition CVD [18,19]. In evaporation deposition, a solid material is placed in a vacu- um and heated until it evaporates. The evaporant molecules strike the cooler wafer and condense into a solid film on the wafer surface.

Thickness of the deposited material is determined by the temperature and the amount of time evaporation is allowed to take place a thickness of 1 mm is typical. The sputtering technique uses positive ions to bombard the cathode, which is coated with the material to be deposited.

The bombarded or target material is dislodged by direct momentum transfer and deposited on wafers, which are placed on the anode. The types of sput- tering systems used for depositions in integrated circuits include dc, radio frequency RF , or magnetron magnetic field. Sputtering is usually done in a vacuum. Chemical vapor deposition uses a process in which a film is deposited by a chemical reaction or pyrolytic decomposition in the gas phase, which occurs in the vicinity of the silicon wafer.

This deposition process is gen- erally used to deposit polysilicon, silicon dioxide SiO2 or simply oxide , or silicon nitride Si3N4 or simply nitride. While the chemical vapor deposition is usually performed at atmospheric pressure, it can also be done at low pressures where the diffusivity increases significantly. Etching Etching is the process of removing exposed unprotected material. The means by which some material is exposed and some is not will be considered later under the topic of photoli- thography.

For the moment, we will assume that the situation illustrated in Fig. Here we see a top layer called a film and an underlying layer. The objective of etching is to remove just the section of the exposed film. To achieve this, the etching process must have two important properties: Selectivity is the characteristic of the etch whereby only the desired layer is etched with no effect on either the protective layer.

Mask Figure 2. Selectivity can be quantified as the ratio of the desired layer etch rate to the undesired layer etch rate as given below. Desired layer etch rate A SA2B 5 2. Anisotropy is the property of the etch to manifest itself in one direction; that is, a perfectly anisotropic etchant will etch in one direction only. The degree of anisotropy can be quantified by the relation given below.

Lateral etch rate A 2. Reality is such that neither perfect selectivity nor perfect anisotropy can be achieved in practice, resulting in undercutting effects and partial removal of the underlying layer as illus- trated in Fig.

There are preferential etching tech- niques that achieve high degrees of anisotropy and thus minimize undercutting effects, as well as maintain high selectivity. Materials that are normally etched include polysilicon, silicon dioxide, silicon nitride, and aluminum.

There are two basic types of etching techniques. Wet etching uses chemicals to remove the material to be etched. Hydrofluoric acid HF is used to etch silicon dioxide; phosphoric acid H3PO4 is used to remove silicon nitride; nitric acid, acetic acid, or hydrofluoric acid is used to remove polysilicon; potassium hydroxide is used to etch silicon; and a phosphoric acid mixture is used to remove metal.

The wet-etching technique is strongly dependent on time and temperature, and care must be taken with the acids used in wet etching as they rep- resent a potential hazard.

Dry etching or plasma etching uses ionized gases that are rendered chemically active by an RF-generated plasma. This process requires significant characteriza- tion to optimize pressure, gas flow rate, gas mixture, and RF power. Dry etching is very similar to sputtering and in fact the same equipment can be used. Reactive ion etching RIE induces plasma etching accompanied by ionic bombardment. Dry etching is used for submi- cron technologies since it achieves anisotropic profiles no undercutting.

Chemical Mechanical Polishing Performing the photolithographic steps on nonplanar surfaces can be challenging. Moreover, maintaining uniform thickness of metal deposited over a surface with abrupt transitions is dif- ficult. The solution is to planarize the surface of the wafer prior to each photolithographic or deposition step.

One means for achieving planarization is to use an oxide appropriately doped so that it will reflow under elevated temperature. Another, and far superior, means for pla- narization is to literally polish the wafer when a flat surface is needed. Modern processes use chemical mechanical polishing CMP to planarize wafers [20].

Photolithography Each of the basic semiconductor fabrication processes discussed thus far is applied only to selected parts of the silicon wafer with the exception of oxidation, deposition, and CMP. The selection of these parts is accomplished by a process called photolithography [12,21,22]. Photolithography refers to the complete process of transferring an image from a photomask or computer database to a wafer.

The basic components of photolithography are the photore- sist material and the photomask used to expose some areas of the photoresist to ultraviolet UV light while shielding the remainder. Photoresist is an organic polymer whose characteristics can be altered when exposed to ultraviolet light.

Photoresist is classified into positive and negative photoresist. Positive photore- sist is used to create a mask where patterns exist where the photomask is opaque to UV light. Negative photoresist creates a mask where patterns do not exist where the photomask is trans- parent to UV light. The photolithographic process involves depositing photoresist on the wafer and conditioning it with time and temperature.

Portions of the photoresist are exposed to UV light. After exposure, the exposed photoresist is hardened through a developing process while the unexposed areas are removed. The hardened photoresist protects selected areas from plasma or acids used in the etching process. When its protective function is complete, the photoresist is removed with solvents or plasma ashing, leaving underlying layers unharmed. This process must be repeated for each layer of the integrated circuit. Figure 2. Photoresist Polysilicon Figure 2.

The process of exposing selective areas of a wafer to light through a photomask is called printing. There are three basic types of printing systems used. They are listed below: This method uses a glass plate a little larger than the size of the actual wafer with the image of the desired pattern on the side of the glass that comes in physical contact with the wafer.

This glass plate is called a photomask. The system achieves high resolution, high throughput, and low cost. Unfortunately, because of the direct contact, the photomask wears out and has to be replaced after 10—25 exposures. This method also introduces impurities and defects, because of the physical contact. For these reasons, contact printing is not used in modern VLSI.

A second exposure system is called proximity printing. In this system, the photomask and wafer are placed very close to one another but not in intimate contact. As the gap between the photomask and the wafer increases, resolution decreases.

In general, this method of pattern- ing is not useful where minimum feature size is below 2 mm. Therefore, proximity printing is not used in present-day VLSI. The projection printing method separates the wafer from the photomask by a relatively large distance. Lenses or mirrors are used to focus the photomask image on the surface of the wafer. There are two approaches used for projection printing: The scanning method passes light through the scaled photomask typically 53 , which fol- lows a complex optical path reflecting off multiple mirrors imaging the wafer with an arc of illumination optimized for minimum distortion.

The photomask and wafer scan the illumi- nated arc. Minimum feature size for this method is approximately 0. The projection printing system most used today is step-and-repeat.

The latest advancements in photolithography, with the goal of increasing resolution, replace the air gap between the lens and the wafer surface with a liquid medium highly puri- fied water. Electron beam exposure systems are often used to generate the photomasks for projec- tion printing systems because of their high resolution less than 1 mm. However, the electron beam can be used to directly pattern photoresist without using a photomask. The advantages of using the electron beam as an exposure system are accuracy and the ability to make soft- ware changes.

The disadvantages are high cost and low throughput. The fabrication steps of a generic submicron CMOS twin-well sili- con-gate process will be described. Fabrication begins with a heavily doped p1 silicon wafer with a lightly doped p2 epi- taxial layer epi layer.

A thin silicon-dioxide region is grown on the surface of the p2 epi layer. Subsequent to this, the regions where n-wells are to exist are defined in a masking step by depositing a photoresist material on top of the oxide. After exposing and developing the photoresist, n-type impurities are implanted into the wafer as illustrated in Fig.

Next, photoresist is removed and p-wells are created using a p-well mask and the photolith- ographic process to define appropriate areas to be implanted. This is followed by oxide removal and subsequent growth of a thin pad oxide layer. The purpose of the pad oxide is to protect the substrate from stress due to the difference in the thermal expansion of silicon and silicon nitride. A layer of silicon nitride is deposited over the entire wafer as illustrated in Fig.

Silicon nitride is used as a stop layer during the CMP step. Photoresist is deposited, patterned, and developed as before, and the silicon nitride is removed from the areas where it has been patterned. The silicon nitride and photoresist remain in the areas where transistors will reside. The regions where silicon nitride remains are called active area AA.

In order to provide isolation between transistors, an etch is performed that cuts trenches between the remaining nitride AA regions as illustrated in Fig. This is followed by a linear oxide growth and a con- formal oxide deposition [Fig. A CMP step removes the oxide, forming a planar surface at the top of the nitride as shown in Fig.

At this stage, the active areas are separated by shallow trench isolation STI regions. Next, using the appropriate p-well or n-well mask and photolithographic steps, p-type and n-type field implants are performed. These will ensure that parasitic transistors are not formed in the field regions.

Nitride is removed. A thin gate oxide is grown followed by a poly- silicon deposition step [Fig. Polysilicon is then patterned and etched, leaving only what is required to make transistor gates and interconnect lines. At this point, the drain and source areas have not been diffused into the substrate. A nitride spacer is formed on the sides of the polysil- icon gates by depositing a thin nitride layer followed by an anisotropic etch [Fig.

To make n1 sources and drains, photoresist is applied and patterned everywhere n-channel transistors are required; n1 is also required where metal connections are to be made to n2 material such as the n-well. After developing, the n1 areas are implanted as illustrated in Fig. The photoresist acts as a barrier to the implant, as does the nitride spacer.

Annealing is performed in order to activate the implanted ions. Annealing is performed, which forms tita- nium silicide TiSi2 at all silicon interfaces [22]. Silicide provides a much lower resistance. Metal 2 Metal 1. Passivation protection layer Metal 5. Silicide is not formed on the nitride spacer. The Ti not inter- facing to silicon is removed using a chemical etch.

Because the titanium silicide does not react with the nitride spacer and is later removed , the resulting silicide is self-aligned with polysilicon and diffusion. Thus, the technique for creating the silicide is called a salicide process meaning a self-aligned-silicide. A new, thick oxide layer is deposited over the entire wafer as.

Contacts are formed by first defining their location using the photolithographic process applied in earli- er steps. Next, the oxide areas where contacts are to be made are etched down to the sur- face of the silicide.

The remaining photoresist is removed. Another CMP step is performed, this time removing the tungsten so that only the tungsten plugs remain where contact holes were formed. Aluminum is deposited to form the Metal 1 interconnect layer.

It is defined photolithographically and subsequently etched removing all unnecessary metal. To prepare for a Metal 2, another interlayer dielectric is deposited [Fig. Again, CMP is performed to planarize the surface of the oxide. Intermetal connections vias are defined through the photolithographic patterning and etch. A CMP step polishes away the tungsten above the surface of the oxide, leaving plugs. Metal 2 aluminum is deposited, patterned, and etched [Fig.

The steps of oxide deposition, CMP, tungsten plug formation, and aluminum metallization are repeated for as many layers of metal as desired. In order to protect the wafer from chemical intrusion or scratching, a passivation layer of oxide or nitride is applied, covering the entire wafer.

Pad regions are then defined areas where wires will be bonded between the integrated circuit and the package containing the cir- cuit and the passivation layer removed only in these areas. To illustrate the process steps in sufficient detail, true relative dimensions are not given i. It is valuable to gain an appreciation of actual scale; thus, Fig. Thus far, the basic twin-well CMOS process has been described. There are a variety of enhancements that can be applied to this process to improve circuit performance.

Prior to forming contact plugs, titanium was deposited and annealed, and titanium sili- cide was formed at all silicon interfaces, including polysilicon. The polysilicide forms a much lower resistance than the polysilicon alone. This is beneficial where low-resistance.

However, analog designers often want to use high-resistance com- ponents and polysilicon is an excellent choice. In order to use the sheet resistance of the polysilicon, the titanium must be blocked from being depositing onto the polysilicon.

This is achieved with an additional mask—silicide block—which does precisely what its name implies. In some processes, the polysilicon is not doped. Intrinsic polysilicon has a very high resistance.

To be useful as an analog component, a mask is used to selectively dope polysil- icon resistors to achieve the desired resistivity. Invariably, analog circuits require high-performance capacitors. There are at least three common ways to achieve useful capacitors: Poly-oxide-poly or simply poly-poly capac- itors are fabricated by an additional step subsequent to the gate-poly step so that two polysil- icon layers lie on top of one another with an intervening thin oxide.

MOM capacitors are formed without any additional processing steps as they are simply capacitors made from the various metal layers that already exist suitably oriented in the layout.

MiM capacitors require the formation of an additional metal layer. It is usually created just prior to the final interconnect layer and sits atop a thin oxide on the second-to-last metal interconnect layer. These capacitor structures are described in Section 2.

When designing analog circuits integrated with complex digital circuitry, one must be careful to avoid interference due to the digital logic—digital noise. Such interference will reduce the performance of sensitive analog signal paths.

There are numerous circuit design techniques that can mitigate digital noise. In addition, there are structural methods to isolate the analog circuits from the digital ones.

Allen 2011 Cmos Analog Circuit Design 3e

One such method is to use deep n-well DNW. The well is driven below the depth of the p-well and the standard n-well. Electrical connection to the DNW is made via n-well and n1 diffusions. Isolation and interference reduction is achieved by connecting the DNW to a quiet supply source e.

As geometries shrink, the breakdown voltages for transistors also go down. Thus, core supply voltages continue to go down e. One solution is to provide transistors with higher breakdown voltages alongside the standard devices.

The primary means for accomplishing this is to offer multiple gate oxides. The process described in this section applies generally to 0. Technologies at 0. The objective of this section is to develop the concepts of the pn junction that will be useful to us later in our study. These include the depletion-region width, the depletion capacitance, reverse-bias or breakdown voltage, and the diode equation. Further information can be found in the refer- ences [23,24]. In this model it is assumed that the impurity concentration changes abruptly from ND donors in the n-type semiconduc- tor to NA acceptors in the p-type semiconductor.

This situation is called a step junction and is illustrated in Fig. The distance x is measured to the right from the metallurgical junction at x 5 0. When two different types of semiconductor materials are formed in this manner, the free carriers in each type move across the junction by the principle of diffusion.

As these free carriers cross the junction, they leave behind fixed atoms that have a charge opposite to the carrier. For example, as the electrons near the junction of the n-type materi- al diffuse across the junction they leave fixed donor atoms of opposite charge 1 near the junction of the n-type material.

This is represented in Fig. Similarly, the holes that diffuse across the junction from the p-type material to the n-type material leave behind fixed acceptor atoms that are negatively charged. The electrons and holes that diffuse across the junction quickly recombine with the free majori- ty carriers across the junction. As positive and negative fixed charges are uncovered near the junction by the diffusion of the free carriers, an electric field develops that creates an oppos- ing carrier movement.

When the current due to the free carrier diffusion equals the current caused by the electric field, the pn junction reaches equilibrium.

In equilibrium, both vD and iD of Fig. The distance over which the donor atoms have a positive charge because they have lost their free electron is designated as xn in Fig. Similarly, the distance over which the acceptor atoms have a negative charge because they have lost their free hole is xp.

In this. Depletion charge concentration cm—3 qND xp c 0 xn x. The depletion region is defined as the region about the met- allurgical junction that is depleted of free carriers. The depletion region is defined as. Note that xp , 0. Due to electrical neutrality, the charge on either side of the junction must be equal. By integrating either side of the junction, the maximum electric field that occurs at the junc- tion, E0, can be found.

This is illustrated in Fig. The voltage drop across the depletion region is shown in Fig. The voltage is found by integrating the negative electric field, resulting in. At room temperature, the value of Vt is The rea- son for this is to avoid confusion with VT, which will be used to designate the threshold volt- age of the MOS transistor see Section 2. Although the barrier voltage exists with vD 5 0, it is not available externally at the terminals of the diode.

When metal leads are attached to the ends of the diode a metal—semiconductor junction is formed. Equations 2. These widths are found as. It can be seen from Eq. Consequently, the depletion region will extend farther into the lightly doped semiconductor than it will into the heavily doped semiconductor.

It is also of interest to characterize the depletion charge Qj , which is equal to the magni- tude of the fixed charge on either side of the junction. The depletion charge can be expressed from the above relationships as.

The magnitude of the electric field at the junction E0 can be found from Eqs. The depletion region of a pn junction forms a capacitance called the depletion-layer capacitance. It results from the dipole formed by uncovered fixed charges near the junction and will vary with the applied voltage.

The depletion-layer capacitance Cj can be found from Eq. Cj0 is the depletion-layer capacitance when vD 5 0 and m is called a grading coefficient. If the junc- tion is fabricated using diffusion techniques described in Section 2. At this value of voltage, the assumptions made in deriving the above equations are no longer valid.

In particular, the assumption that the depletion region is free of charged carriers is not true. If both sides of the pn junction are heavily doped. Cj is 9. Using these values in Eq.

For silicon. The current in most breakdown diodes will be a combination of these two current mechanisms. The first current mechanism is called avalanche multipli- cation and is caused by the high electric fields present in the pn junction. This increase is due to two conduction mechanisms that can take place in a reverse-biased junction between two heavily doped semiconductors.

At room temperature. If iR is the reverse current in the pn junction and vR is the reverse-bias voltage across the pn junction. Zener breakdown is a direct disruption of valence bonds in high electric fields. The excess of minority- carrier concentration on each side of the junction is shown by the shaded regions. The forward bias causes minority carriers to move across the junction where they recombine with majority carriers on the opposite side.

Zener diodes can be fabricated where an n1 diffusion overlaps with a p1 diffusion. We note that these values are essentially equal to the intrinsic concentration squared divided by the donor or acceptor impurity atom concentration. If vD is zero. The majority-carrier concentrations are much larger and are not shown on this figure. This relationship is given by the diffusion equation expressed below for holes in the n-type material. The diode voltage—current relationship can be derived by examining the minority-carrier concentrations in the pn junction.

The current that flows in the pn junction is proportional to the slope of the excess minority-carrier concentration at x 5 0 x9 5 0. We note that this excess concentration starts at a maximum value at x 5 0 x9 5 0 and decreases to the equilibrium value as x x9 becomes large.

If vD is negative reverse biased. Note that the Zener diode is compatible with the basic CMOS process although one terminal of the Zener must be either on the lowest power supply. As vD is increased. The excess holes in the n-type material can be defined as.

The value of the excess concentration at x 5 0. Substituting Eq. At equilibrium. Equation 2. These concepts will be very important in determining the characteristics and performance of MOS active and passive components. The two p1 regions are called drain and source. Multiple n-wells can be fabricated on a single circuit. From Eq. Ln 5 10 mm. At the surface between the drain and source lies a gate electrode that is separated from the silicon by a thin dielectric material sil- icon dioxide.

This "choice" is not necessarily that of the designer but of industry trends that want to use standard technologies to implement analog circuits along with digital circuits. As a result, the first edition of CMOS Analog Clrcuil Design fulfilled a need for a text in this area before there were any other texts on this subject.

It has found extensive use in industry and has been used in classrooms allover the world. Like the first edition, the second edition has also chosen not to Inelude BIT technology. The wisdom of this choice will be seen as the years progress.

The second edition bas been developed with the goal of extending the strengths of the first edition, namely in the area of analog circuit design insight and concepts. This blending ball occurred over the past 15 years in short courses taught by the first author. Over 50 short courses have been taught from the first edition to over l engineers allover the world.

In these short courses. In addition to the industrial input to the second edition. The first edition had problems. The second edition bas over problems, and most of those are Dew to the second edition. The audience for the second edition is essentially the same WI for the first edition.

The second edition should continue to be of value to both new and experienced engineers in industry. The principles and concepts discussed should never become outdated even though technology changes.

The second audience is the classroom. Out hope is that the second edition win provide both instructors and students with a tool that will help fulfill this demand. In order to help facilitate this Objective, both authors maintain websites lhal permit the downloading of short course lecture slides, short course schedules and dates, class notes, and problems and solutions in pdf format, More information can be found at www. Allen and www.

The second edition has received extensive changes. These changes include the moving of Chapter 4 of the first edition to Appendix B of the second edition. In the 15 years since the first edition. A msjor change has been the incorporation of Chapter 9 on switched capacitor circuits. There are two reasons for this. Switched cepacitors are very important in analog circuits and systems design, and this information is needed for many of the analog-digital and digital-analog converters of Chapter lO.

Chapter 11 of the first edition has been dropped. There were plans to replace it with a chapter on analog systems including phase-locked loops and VCOs, but time did nOI allow this to be realized.

The problems of the second edition are organized into sections and have been designed to reinforce and extend the concepts and principles associated with a particular topic. Chapter 1 presents the material necessary to introduce CMOS analog circuit design. This chapter gives an overview of the su. This chapter alsn includes a section on the impact of integrated circuit layout.

This portion of the text shows that the physical design of the integrated circuit is as important as the electrical design.

Chapter 3 introduces the key subject of modeling, which is used throughout the remainder of the text to predict the performance of CMOS circuits. Computer simulation can be used to more exactly model the circuits but will not give any direct insight or understanding of the circuit.

This chapter also discusses computer simulation models. This topic is far too complex for the scope of this book; but some of the basic ideas are presented so that the reader can appreciate computer simulation models.

Chapters 4 and 5 represent the topics of subcircuits and amplifiers that will be used to design more complex analog circuits. These subcircuits permit the illustration of important design concepts such as negative feedback, design tradeoffs. Finally, this chapter presents independent voltage and current references and the bandgap voltage reference.

These references attempt to provide a voltage or current that is independem of power supply lllJd temperature. Chapter 5 develops various types of amplifiers. These amplifiers are characterized from their large-signal and small-signal performance, including noise W1d bandwidth where appropriate. The categories of amplifiers include the inverter, differential.

The last section discusses how high-gain amplifiers could be implemented from the amplifier blocks of this chapter. Chapters 6, 7, and 8 represent examples of complex analog circuits.

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Chapter 6 introduces the design of a simple two-stage op amp. This op amp is used to develop the principles of compensation necessary for the op amp to be useful. The two-stage op amp is used. This chapter also examines the design of the cascode op amps, particularly the folded-cascode op amp. Macromodels can be used to more efficiently simulate op amps at higher levels of abstraction.

Chapter 7 presents the subject of high-performance op amps. In this chapter various performances of the simple op amp are optimized. The topics include buffered output op amps, high-frequency ep amps, differentialoutput op amps, low-power op amps, low-noise op amps. Chapter 8 presents the open-loop comparator, which is an op amp without compensation.

This is followed by methods of designing this type of comparator for linear or slewing responses. Methods of improving the performance of open-loop comparators, including autozeroing and hysteresis. Chapters 9 and 10 focus on analog systems.

Chapter 9 is completely new and presents the topic of switched capacitor circuits. The concepts of a switched capacitor are presented along with such circuits as the switched capacitor amplifier and integrator. Methods of analyzing and simulating switched capacitor circuits are given, and first-order and second-order "yt PREFACE switched capacitor circuits are used to design various filters using cascade and ladder appreaches.

Chapter 9 concludes with anti-aliasing filters. Digital-ana1og converters are presented according to their means of scaling: the reference and include voltage.These passive components include the capacitor and the resistor. They are listed below along with their impact.

The material of the third edition is more than sufficient for a week course. To address this dilemma. The input voltage. Annealing is performed, which forms tita- nium silicide TiSi2 at all silicon interfaces [22].

Intermetal connections vias are defined through the photolithographic patterning and etch. An analog signal is a signal that is defined over a continuous range of time and a continuous range of amplitudes.